The present invention relates to a circuit configuration of a sense amplifier and an output circuit designed to achieve high speed in operation of a dynamic random access memory (DRAM).
A typical conventional DRAM employs a basic circuit configuration such as that shown in FIG. 1 (see "LSI Handbook", pp. 486 to 498). More specifically, a memory cell (MC) is a dynamic memory cell consisting of an insulated-gate field effect transistor (MOS transistor) and a storage capacitance Cs. Although the circuit shown in FIG. 1 employs a 1TR-type cell, a 3TR- or 4TR-type dynamic cell is also employed in some cases. A memory cell array (CA) is formed by arranging a plurality of such cells in a matrix. FIG. 2 is a time chart showing the operation of the DRAM. The operation of the DRAM will be explained below with reference to FIGS. 1 and 2.
The reference symbol CS in FIG. 2 denotes a clock signal on the basis of which various pulses are generated inside the chip. FIG. 2 exemplarily shows a case where, when the CS is at a high level (High), the DRAM is in a stand-by state, whereas, when the CS is at a low level (Low), the DRAM is in an operating state. Under certain circumstances, it may be possible to adopt a method wherein changes in an address input are sensed, and various pulses are generated on the basis of the sensed changes, as shown in "'84 ISSCC", pp. 276 to 277. When the DRAM is in a stand-by state (CS: High), data lines D and D are set at a voltage V.sub.H (e.g., 1/2 Vcc, where Vcc is supply voltage) by the operation of a precharge circuit (PC) in advance. When the DRAM is in an operating state (CS: Low), the precharge circuit is off, and thereafter, a predetermined word line W is selected in response to an address input. In consequence, a MOS transistor for switching of a memory cell connected to the selected word line W turns on, and the data line potential changes in accordance with the amount of charge accumulated in the storage capacitance Cs, that is, data stored therein. Thereafter, the sense amplifier SA and an active restore circuit AR are activated to amplify the data line potential to a level which is substantially equal to the supply voltage Vcc or the ground-level. Although SA and AR are herein shown separately from each other due to the convenience of explanation, these may be given a general term "sense amplifier", and various circuit configurations may be employed therefor. Then, a predetermined .phi..sub.Y is selected in response to an address signal to thereby turn on MOS transistors MY.sub.1 and MY.sub.2 or switching. Thus, a voltage difference is produced between a pair of common data lines I/O and I/O in accordance with the respective potentials of the two selected data lines D and D. This voltage difference is amplified by a main amplifier MA. For writing, a write circuit WC is controlled by .phi..sub.W so as to allow the pair of common data lines I/O and I/O an have potentials corresponding to data inputs di and di, respectively, thereby writing desired data in a memory cell via a selected data-line. It should be noted that the input/output signal levels in FIG. 2 are set on the assumption that they are used for a TTL (Transistor-Transistor-Logic) interface, and in the case of an ECL (Emitter Coupled Logic) interface, input/output signal levels may be set as follows: -0.9 V for the high level; -1.7 V for the low level; GND (0 V) for the positive side of the supply voltage; and V.sub.EE (-5.2 V) for the negative side of the supply voltage. CS is a control signal for the memory, as described above, which switches a stand-by state and an operating state one from the other. In an address multiplexing memory, two signals, known as RAS (Row Address Strobe) and CAS (Column Address Strobe) are employed in place of CS (Chip Select).
In the conventional DRAM, a signal which is read out to the common data lines is amplified by a main amplifier and an output circuit, which employ MOS transistors. It is a known fact that a MOS transistor has a relatively small amount of change in drain current with respect to a change in the gate voltage, that is, the mutual conductance g.sub.m of the MOS transistor is relatively small. In consequence, it was impossible, in the prior art, to achieve both high sensitivity and high speed in amplification of the signal read out to the common data lines.